In the past decades, the semiconductor industry has been improving the performance and density of integrated circuits primarily by shrinking the size of the electronic elements within the circuits. However, a number of barriers are becoming evident which increase the difficulty of making further reduction to the size of these elements. One potential solution for increasing the performance and planar density of integrated circuits is to create three dimensional circuits which contain multiple layers of interconnected circuitry.
Interconnections between a base plane and overlying circuit layers provide power, read/write access, and programming capabilities throughout the three dimensional circuit. However, these interconnections can consume valuable area within the circuit, add significant levels of complexity to the layout, and reduce the bit density of the circuit.
Throughout the drawings, identical reference numbers designate similar, but not necessarily identical, elements.